1. Field of the Invention
The invention relates to the field of telephone systems and in particular to telephone systems in which multiple stations may be operated on a single shared telephone line.
2. Description of the Prior Art
The System
Home and small office telephone systems are typically purchased and operated by the telephone user. In addition, the telephone user or the owner of the building in which the telephone system is installed, is similarly responsible for the installation and maintenance of the internal telephone lines beginning at the telephone company line terminal at the entry point to the building. Very commonly, the internal telephone wiring which is available in a home or small office is a single line system. In other words, while there may be multiple telephone jacks, each of the jacks are coupled in parallel to a single telephone line within the structure. Therefore, only one telephone conversation at a time may be carried on the line and if two handsets are picked up, the power on the line is distributed between the two activated handsets with a consequent loss of audible volume. Additionally, the communication as well as the central office link must be generally held in common between the two participants.
A number of schemes have been attempted for expanding the communication capability of a single internal telephone line network, most of which involved various voice band multiplexing schemes. As the features and complexity of the telephone network increases, greater demand is placed upon the multiplexing system. The complexity of the multiplexing scheme can become prohibitive when the system must be full featured. For example, when the system must provide an automated operator to provide voice message answering of incoming calls, special handling of fax, phone, modem and answering machines at the telephone stations, extension dialing, a host of separate business phone features and fax features, and accommodate a large number of phone stations all incorporated in an economical package which easily lends itself to expansion and modification, the prior art has failed to provide practical solutions. The difficulty arises from many reasons including the following: (1) The expense and labor involved in wiring or rewiring the facility if a star wire system is used (a separate wire to each phone); and (2) the complexity and technical difficulty in implementing a digital or frequency band (AM, FM, etc.) form of sharing a single common line. Finally, the high communication and computer overhead time which is required in a multiplexing system to handle multiple features and stations with complete flexibility and adaptability. The amount of digital communication which must be carried on often becomes prohibitive and the system fails during peak periods or unusual demand scenarios.
Many multiple wire (star wire) as well as some two-wire small phone systems utilizing a master controller and multiple station controllers are known in the art. The multitude of star wire systems suffer from both the inherent wiring complexity as well as the following problem. One typical two wire system is the Model 8002 MCD base key telephone system unsuccessfully offered by Rockwell. In such systems, a sophisticated processor is not only required in the master controller, but also at each station which adds to the cost and complexity of the system. An architecture which is built upon multiprocessing makes changes in the system difficult since modifications must be made in both the controller program and in the station programs. Communication between these multiprocessors is complex and when the number of stations increases, overall communication can become very slow during busy periods. Only a few features can be changed remotely since again most of the features require changes in both station and controller programs.
In the Rockwell system, a mix of voice channels, digital channels and a reference signal on a twisted pair telephone line, using double side band suppressed carrier with amplitude modulated signals was employed. However, the Rockwell system did not define the structure of digital data communication, nor did it remove the requirement for a separate control processor in every station. Therefore, although it did allow multiple signals on a single twisted pair telephone line, it did not provide any simplification to the complexities of multiprocessing nor solve the inflexibilities inherent in multiprocessing architectures. Additionally, this product suffered from severe noise, phase lock, and synchronization problems which eventually doomed it to failure.
Therefore, what is needed is a single twisted pair, multichannel telephone system which can be economically and easily adapted to a home or small business and which has the power and flexibility to perform the functions discussed above without undue complexity, expense or susceptibility to failure under heavy demand or unusual use scenarios. Additionally, it needs to solve the critical noise and synchronization problems inherent in such a system without resort to a full digital (and very expensive) solution.
Simplified Processor
Conventional general purpose processors typically operate on a program stored in a read only memory by means of an instruction counter in order to read the stored instructions in sequence or according to a sequence with programmed jumps. This architecture is relatively complex, requires large numbers of transistors to implement and will therefore use a large area of a chip when integrating this function, and is time consuming of real time communication cycle time. The disadvantages of such a processor are particularly burdensome in an application where general programmability is not required.
What is needed is an architecture and method of operation for a processor which is more usable for applications that require only a limited number of operations and that avoids the overhead and timing disadvantages of a general purpose processor.
Communication Signaling Scheme
In a typical prior art small telephone system, a separate pair of wires is coupled from a control unit or master phone to each remote station or telephone handset. This type of system is commonly referred to as a xe2x80x9cstar wirexe2x80x9d system. The control unit determines where the message is coming from and where it will be going according to which pair of wires is selected. This system has the disadvantage that there is a need to provide a separate wire pair for each remote station connected to the control unit and thus eliminates the use of standard house telephone wiring since conventional home wiring typically connects to all the extensions or telephone stations in parallel on a single pair of wires.
The prior art has also devised a scheme in which a single pair of wires is shared between multiple remote stations connected to a control unit. The control unit or master phone manages the telephone network by using a message based protocol. Whenever a phone call or message is to be sent, the transmitting unit, regardless of whether it is a remote station or control unit, will initiate a message in the network by sending an initial data protocol which will define the transmitter and recipient of the message. This type of message based protocol is subject to slow downs or lock up as the number of remote units and systems activity increases.
What is needed is a communication protocol for a small telephone system which is not subject to the limitations of the prior art. In particular, the protocol should eliminate the need in the system to establish a handshake protocol every time a message is sent in either direction to avoid slow downs during active communication periods between a plurality of units. Such a protocol should also allow serial digital data to be transmitted over the same line in burst format without affecting signaling speed so that components such as a display can be serviced quickly without affecting signaling response time. Additionally, a good error correction scheme must be implemented without affecting signal response time. Serial data should be quickly transferred for display or use in other serial communication network applications regardless of the direction of transfer.
Voltage Controlled Crystal Oscillator
Voltage controlled crystal oscillators in the prior art generally do not use MOSFETs to modulate the output impedance of the amplifier stages in the oscillator to shift the phase of the output in order to change the frequency of the crystal controlled oscillator. In addition, prior art voltage control oscillators are generally not designed to be easily integrated in large communication circuits.
What is needed is a crystal controlled voltage oscillator using phase shift techniques in which the frequency of oscillation can be adjusted within a tight and stable range and which has a topology suited to integrated circuitry and that utilizes a small chip area.
Light Emitting Diode Driver Circuit
The standard method for driving multiple light emitting diodes (LEDs) is to drive them in parallel through a series resistance and switched by appropriate logic signals. The current through any light emitting diode is determined by the value of its corresponding series resistor when the logic switch is closed which is also in series with the diode. When all the light emitting diodes are on, the current is additive and may be substantial depending upon the number of LEDs.
Therefore, what is needed is a circuit in which the total current used to drive a bank of light emitting diodes can be held constant and limited for lower power applications. Further, if the mechanism using the diodes is line powered on a line also used for communication the amount of noise which switching of the current through the light emitting diodes places upon that communication line should be avoided as much as possible as it could interfere with that communication. In addition, the current supplied to each LED must be maintained as constant as possible in order to maintain consistent LED brightness within a multiple bank of LEDs regardless of how may of the LEDs may be lit. These attributes are difficult to maintain with parallel LED switching.
Automatic Timing Compensation for a Communication Line
Telephone systems which use an internal telephone cable and which carry voice and/or data modulated signals at high frequencies are characterized by line delays between signals transmitted between the control unit and the station unit and between two station units. In order to compensate for these inherent line delays, the prior art has devised circuits for advancing the transmission signal or delaying the received signal a fixed average amount given the line length specification variations if the line delay is above a predetermined minimum and otherwise accepting smaller line delay inaccuracies.
Another method used in the prior art is to manually adjust the compensation components tied to the line at the time of installation in order to attempt to cancel out line delay variations.
What is needed is some type of circuit which provides for automatic adjustment to the transmission signal to avoid line delays, a circuit which can be implemented at low cost and which adjusts for potential load changes such as may occur when a new station is plugged in.
A Low Cost Adaptive Echo Balance Methodology
Whenever there are four-to-two wire conversions in a telephone system, there is an echo back of the transmitted signal which must be given consideration in the design of the system. In such applications where echo in not critical, the provision of a fixed component balance network is usually a satisfactory solution. In other applications where echo cancellation is more critical, normally a signal processor particularly adapted to cancel the echo is employed.
What is needed is some type of apparatus and methodology wherein echo cancellation can be achieved in applications where a fixed network would not provide a satisfactory solution, but which does not require the more expensive compensation based upon a digital signal processor for echo cancellation.
A Two-Wire Twisted Pair, Multiple Signal, Capacitor Coupled, Communication Line Interface
A typical prior art means for interfacing multiple signals onto an internal (inside the house or office) twisted pair communication line is comprised of a transformer across the primary of which the internal communication line is connected and across the secondary of which a transmit buffer and receive buffer are provided for bidirectional communication with internal circuitry. The internal communication line could be a telephone cable within a home or office and the internal circuitry to which it would be coupled would be a key telephone circuit or handset. A plurality of such transmit and receive circuits could be coupled in parallel across the secondary of the transformer to couple multiple sources at the same location to the internal communication line through a single interface. Each source to be coupled to the internal communication line at different locations of course requires a separate transformer and in a typical system, a multiplicity of transformers are used corresponding to the number of remote sources.
The large number of transformers necessary for a useful system creates a large accumulation of magnetizing inductance, leakage inductance, core saturation and resonance which degrades the communication transmission for relatively wide bandwidth signals and thereby severely limits the number of interfaces that can be reliably coupled to the internal communication line.
Therefore, what is needed is a circuit and method to provide interfacing for a two-wire twisted pair that will support: (1) multiple signals being communicated on the line at the same time through the same interface such as a reference frequency, digital signaling data, and/or voice modulation at different frequencies; (2) signals being communicated through several interfaces simultaneously from different locations on the line; (3) large variation in line load and other system loads without significant signal degradation; (4) the supplying DC power over the same lines; (5) a common low impedance line load; and (6) echo cancellation to eliminate false data from being transferred.
Telephone Line Interface
A typical telephone line interface uses a transformer to couple to the central office lines and two buffer amplifiers coupled to the secondary of the transformer to provide a signal OUT and signal IN to the equipment being interfaced whether a common telephone or a sophisticated PBX system. An example of such a prior art line interface unit is shown in FIG. 21 and includes transformer 338 with a secondary 340 and primary 342. Amplifier 344 is used to generate the signal OUT and is coupled to secondary 340 while amplifier 346 drives the secondary from the signal IN. Summing resistors 348 associated with the transmit amplifier 344 sums the input signal and the output signal to thereby provide basic echo cancellation. Output drive amplifier 346 and its associated summing resistors 350 and output resistor 352 drive the appropriate output signal through the transformer 338 onto the telephone lines coupled to primary 342.
The implementation of FIG. 21 suffers from an erroneous echo signal due to reactive parameters associated with the greatly varying telephone line characteristics and transformer 338.
A Piezo Driver Using Voltage Doubling and CMOS Techniques
A typical prior art piezo circuit uses switched positive and/or negative supply voltages which are available within the system, or alternatively some type of power supply which is coupled to the piezo driver to provide a higher voltage which is switched in when needed. This is a relatively expensive and space consuming solution to the problem of providing a higher voltage to a piezo ringer than is normally available in a telephone circuit.
Therefore, what is needed is some means for applying a higher voltage to the piezo element without the need of providing an additional higher voltage power supply so that sound volume improvement can be provided in a manner compatible with integrated circuit technology at low cost.
Voltage Limiter
Prior art voltage limiters for amplifiers typically use cascaded diodes coupled in parallel across the input and output of the amplifier in one or both directions to limit the voltage range of the amplifier. The linear range of such cascaded diodes is, however, limited.
Therefore, what is needed is some type of circuitry in which voltage limitation across an amplifier can be achieved over an extended linear dynamic range, closer to the voltage limit points.
Line Powering for Two-Wire Twisted Pair, Multiple Signal, Capacitor Coupled Communication Line Interface
When remote electronic devices are powered by the communication line, consideration must be given to the noise generated by providing power on the same wires as the communication signals. In a typical house telephone line, this type of noise is typically not severe since all the operating devices share the same communication channel and the same parties to the communication. In that case, any noise is synchronous with a voice conversation in progress and is generally not harmful. In those cases where the line is shared between devices having signals which are incompatible, such as in a telephone and modem communication, the user generally does not use the incompatible devices at the same time and thereby avoids the conflict. However, in the case of simultaneous, unrelated communication of multiple devices sharing the same wire, line powering becomes very complicated and the solutions are costly if low noise is required.
In a two-wire line, one wire is provided at a positive voltage and the other at negative voltage to provide a constant current flow to the remote stations. In order to energize such a system, the voltage must first be placed across the two wires of the line by a line power source. Then the remote stations must have means for pulling power from the line at a constant predictable rate in order to minimize the possibility of generating noise on the line which might interfere with the communication.
Digital and analog circuits typically utilize a constant voltage and have variable current demands. In addition, many such circuits require several different voltages to be supplied each with different current demands at different times. It is further desirable to minimize the different types of voltage supplies needed and to provide a current balance between the positive and negative rails as much as possible in order to avoid drift of the voltage supplies relative to the voltages of the supplying two-wire lines.
Therefore, what is needed is some sort of apparatus and methodology for line powering whereby multiple devices can employ a common line with multiple channels having unrelated signals, which devices communicate with different parties without the generation of noise through the line powering which interferes with any of the communication.
The System and the Chip
The invention is a telephone communication system for communication between a plurality of exterior telephone lines and a single common in house two-wire line. The system comprises a control unit for coupling to the plurality of exterior telephone lines and for controlling communication between the plurality of exterior telephone lines and the common two-wire line. A plurality of station units are coupled remotely throughout the building to the common two-wire line. Each of the station units selectively communicates on one of a plurality of voice bands or channels with any one of the exterior telephone lines or with another station under the control of the control unit. Each of the station units communicates digital control and data information with the control unit on a separate AM modulated frequency band or channel on the common two wire line. The control unit communicates on this digital channel with the plurality of station units in a time frame subdivided into a plurality of tine slots. A specified portion of each time slot is reserved for control communication between the control unit and each one of the plurality of station units. All control communication between each one of the station units and control unit occur within the selected portion of the time slot within each time frame. As a result, control communication on the single common two-wire line is effected without requiring complex control hardware within the control unit or station units. Communication between the station units and the control unit is on at least one AM digital channel.
The control unit generates a reference frequency to which the plurality of station units are synchronized. The plurality of station units and the control unit are synchronized with each other through phase lock synchronization to the reference frequency using crystal controlled VCO.
The system further comprises a plurality of modulating interfaces in the control unit. Each modulating interface, contained in part of a MAN chip, services a separate one of the exterior telephone lines. One of the plurality of modulating interfaces serves as a master and the remaining ones are slaved to the master.
The plurality of modulating interfaces (MAN chips) in the control unit and in the station units are identical, but operated in different modes according to their respective operational position within the system so that a system based on a single integrated circuit is provided.
The control unit also contains the central microprocessor which is programmable and all communication features between the control unit and the plurality of stations and their relationship with the exterior telephone lines are stored within this control unit processor so that the entire system may be modified by modifying the programs stored in the control unit. Because of this, the system may be more easily changed and may even be remotely modified through the exterior telephone company lines coupled to the control unit.
The control unit communicates with the plurality of station units through a digital data channel. The digital data channel has two digital signals simultaneously communicated in phase quadrature through phase shifted keying.
The digital data channel is full duplex and serial digital data is communicated through a portion of the time frame. The remaining portion of the time frame is used for communication of control information between the control unit and the plurality of station units.
The control unit and plurality of station units by means of their MAN chips encode, generate and communicate control and status information onto the common two wire line over the digital data channel.
The plurality of voice channels are simultaneously (with the above reference signal and digital data channel) communicated onto the common two wire line and the control unit comprises a circuit for programmably vectoring a selection of the voice channels in order to selectively network the plurality of voice channels among the station units coupled to the single common two wire line.
The control unit and plurality of station units by virtue of the MAN chip contained within each further comprise a controllable input/output port programmably capable of logic switching and sensing, keyboard and display control, as well as tone and pulse generation.
The control unit and plurality of station units by virtue of the MAN chip contained within each comprise circuitry for interfacing with a general purpose microprocessor for bidirectional exchange of data, control, and status information with the microprocessor.
The control unit also contains circuitry to detect various tones and pulses as well as generate voice messages in order to provide for a full featured business telephone system capability, although these features are not unique of themselves.
A Simplified Bus Oriented Processor Using a Fixed Time Slot Protocol
The invention also includes a bus oriented processor comprising a data bus having fixed time slot access with respect to devices on the bus that are peripheral to the processor. Each peripheral device is accessed through fixed and unique portions of timing frames on the data bus. A universal logic unit is coupled to the data bus. The universal logic unit performs a predetermined assortment of operations on data read from or written to the data bus during fixed time slots within the timing frame.
The processor further comprises a plurality of registers coupled to the data bus. Each of the registers is read from or written into during selected and fixed time slots within the timing frame. A corresponding plurality of combination and logic circuits are provided. Each combination and logic circuit is coupled to one of the registers and to the universal logic unit for receiving a compare/carry control signal, CMPCRY, indicative of whether or not a compare or carry occurred or not during a corresponding operation within the universal logic unit.
The processor further comprises a plurality of bit memory circuits for storing bit flag and other machine state flags, and a corresponding plurality of combination and logic circuits. The corresponding combination and logic circuits are coupled to the timing and control bus. A logical combination is detected by the corresponding combination and logic circuit from the timing and control bus and the CMPRY, and the bit flag is stored within the bit memory circuit for generating a conditional logic signal.
The universal logic unit performs only two basic types of instructions. The first type are compare instructions and the second type of instructions are incrementation/decrementation instructions.
Each time slot is comprised of dedicated cycles. Each cycle and portion of cycle within each time slot is dedicated to bus precharge, selective data transfer from the bus or selective data transfer to the bus in a fixed sequential order so that bus voltage levels can be maintained and contention can be avoided.
The invention is also a method of operating a processor to which an instruction is communicated. The method comprises the function of repetitively performing a sequence of timed steps. The steps include the following: precharging the data bus; selectively reading a first data signal from the data bus during a first dedicated time cycle depending upon the instruction; precharging the data bus; selectively reading a second data signal on the data bus during a second dedicated time cycle according to the instruction; selectively performing one of a predetermined number of operations on the first and/or second data signal during the second and beginning of the third dedicated time cycle according to the instruction; selectively writing the result of the operation during the third dedicated time cycle according to the instruction; and selectively generating a logic signal, CMPCRY, during the third dedicated time cycle according to the instruction and according to the results of the step, performing a control action such as the step of writing the data into a register.
The step of performing the instruction consists of one of the steps of:
comparing the first and second data signals and selectively incrementing the first data signal;
comparing the first and second data signals and selectively decrementing the first data signal;
incrementing the first data signal; and
decrementing the first data signal.
Communication Signaling Scheme
The invention is an improvement in a method for communicating over a single two-wire cable with a plurality of stations comprising the step of bidirectionally communicating with the plurality of stations in a sequence of time frames. Each of the time frames is divided into a plurality of time slots corresponding to the plurality of stations. Each one of the time slots is dedicated for communication to a specified one of the plurality of stations. The step of bidirectionally communicating comprises communicating serial digital data (that is stream format communication data) in at least one portion of the time slot and communicating signaling data (that is control information) in at least another portion of the time slot. Each of the time frames having a frame sync included therein to which the station units synchronize communication on the two-wire cable. As a result, efficient data signaling with the station units is performed without substantial dependence on system activity.
The improvement further comprises the step of communicating a reference signal to the station units from the control unit as a single timing signal against which the time frames of each of the station units are synchronized by circuitry which senses the frame sync.
The improvement further comprises the step of performing for each station unit within its corresponding dedicated time slots in consecutive frames an echo back communication protocol as determined by detected communication errors and selectively correcting the communication errors in signaling data.
The signaling data is correlated in the bidirectional communication with a specified register within the station unit receiving the communication so that the bidirectional communication is easily implemented in hardware.
Each time slot is comprised of three byte cycles. Two of the cycles are dedicated to serial data and the third of the cycles is dedicated to signaling data.
Each of the time slots is divided into a sequence of dedicated byte cycles. Each of the cycles is dedicated to distinguishable groups of signaling data and serial digital data relating to communication of the control unit with the station unit. The signaling data is directed to or from separate and specific registers within the station unit.
Voltage Controlled Crystal Oscillator
The invention is an integrated circuit, crystal controlled voltage controlled oscillator comprising a plurality of phase shifting amplifiers in combination with a crystal controlled feedback loop coupled across the plurality of phase shifting amplifiers. The phase shifting amplifiers are voltage controlled. A bias tracking circuit maintains a constant bias voltage within the plurality of phase shifting amplifiers regardless of any control voltage applied to the phase shifting amplifiers. As a result, control of output frequency of the voltage control oscillator is maintained over an extended range without saturation of the phase shift amplifiers.
Each phase shifting amplifier is comprised of a CMOS inverter having an output node, a capacitor coupled to the output node and a voltage controlled output impedance modulating circuit for modulating the impedance of the output node and phase shift at the output node. The capacitor is a pair of CMOS shunt transistors coupled to the output node.
More specifically the plurality of phase shifting amplifiers comprises three CMOS inverters. Each inverter has an output node. The CMOS inverters are coupled serially with each other to form a cascaded chain of a first, second and third inverter. Two pairs of CMOS shunt transistors comprise a capacitor. One pair of the CMOS shunt transistors is coupled to each the corresponding output nodes of the first and second inverters. Two CMOS voltage controlled modulating circuits coupled to the output nodes of the first and second inverters to modulate the dynamic impedance of the output nodes of the first and second inverters to control the phase shift of the voltage at the output of the third inverter. The output of the third inverter is coupled to the crystal controlled feedback loop so that the resonant frequency of the crystal controlled feedback loop is in turn controlled by the phase shift at the output node of the third inverter. The voltage controlled oscillator has a fundamental frequency determined by a voltage signal applied to the CMOS impedance modulating circuit.
The voltage controlled oscillator is fabricated in a CMOS integrated circuit so that the first and second inverters and the two corresponding CMOS impedance modulating circuits have operational characteristics dependent upon integrated circuit process parameters and wherein the two corresponding CMOS shunt transistors are coupled to the corresponding first and second output nodes to produce excess phase lag to cancel at least in part the effect of the integrated process parameters upon the operating characteristics.
The bias tracking circuit comprises a matched dummy circuit matching in operational characteristics the two CMOS output impedance modulating circuits. The dummy circuit has a dummy node. A control circuit is coupled to the control voltage applied to the voltage controlled oscillator. The control circuit drives the dummy circuit to maintain the dummy node free of displacement current as the control voltage changes. The control circuit is coupled to the CMOS voltage controlled modulating circuit to essentially maintain the output nodes of the first and second inverters free of displacement currents as the voltage control signal changes, so that self-bias of the phase shifting amplifiers is substantially independent of the control voltage.
The three inverters are matched and the control circuit comprises two dummy inverters, each matching the three matched inverters. An operational amplifier is included. Each of the matched dummy inverters within the control circuit is coupled to one of two inputs of the operational amplifier. The dummy output node is fed back to one of the inputs of the operational amplifier to maintain the dummy node at a net zero displacement current by driving the dummy circuit with the output of the operational amplifier to maintain the node at a net zero displacement current while the control voltage is applied to the dummy circuit. The output of the operational amplifier is are coupled to each of the CMOS voltage controlled modulating circuits to similarly drive each of the CMOS voltage controlled modulating circuits to maintain the corresponding first and second output nodes at a net zero displacement current.
The invention is still further characterized as a method for operating a voltage crystal controlled oscillator in a CMOS integrated circuit comprising the steps of receiving an input signal at an input node; and phase shifting the input signal to generate a phase shifted output at an output node by circuit of voltage controlled phase shifting circuits. The phase shifted output signal from the output node is fed back to a crystal controlled resonant circuit. The output of the crystal controlled resonant circuit is fed back to the input node. Each of the prior steps is repeated to create a regenerative oscillator. The fundamental frequency of the oscillator is determined by the crystal controlled feedback circuit. The phase shift introduced at the step of phase shifting with a voltage control signal is modified to change the fundamental frequency of oscillation. The DC bias of the phase shifting circuits used in the step of phase shifting is maintained constant as the voltage control signal changes to extend the range of voltage control adjustment of the fundamental frequency of the oscillator without saturating the inverting amplifiers.
The step of maintaining self-bias comprises the steps of applying the voltage control signal to a dummy circuit matching the phase shifting circuit; generating a gate control signal which when applied to the dummy circuit maintains self-bias of the dummy circuit independent of the voltage control signal; and applying the gate control signal to the voltage controlled phase shifting circuits within the voltage control oscillator.
The method further comprises the step of increasing the voltage range output from the phase shifting circuits by applying CMOS shunt capacitive transistors to the output constructed of the gates of CMOS FET transistors similar to the inverting amplifier FETs themselves.
The method further comprises the step of increasing the degree of phase shift during the step of phase shifting in the voltage controlled oscillator by providing two cascaded phase shifting voltage controlled circuits driven in parallel by the voltage control signal and coupled in series to provide an excess phase shifting lag within the voltage controlled oscillator of approximately 90 degrees.
Light Emitting Diode Driver Circuit
The invention is a circuit for driving a plurality of light emitting diodes comprising a series circuit of the plurality of light emitting diodes. A plurality of switches is provided in series circuit. Each one of the switches is coupled in parallel across a corresponding one of the plurality of light emitting diodes so that the series circuit of light emitting diodes and series circuit of switches together collectively comprise a ladder network. A constant current source is coupled in series with the ladder network. As a result, the plurality of light emitting diodes are efficiently driven with a substantially constant light emission intensity with a reduced maximum energy.
The circuit further comprises a plurality of the series circuits of light emitting diodes and corresponding plurality of the series circuits of switches to form a corresponding plurality of ladder networks. Each of the ladder networks are coupled in parallel. The circuit further comprises a gate control circuit coupled to each of the ladder networks for selectively coupling one of the corresponding parallel ladder networks to the constant current source. The gate control circuit selectively switches in sequence each of the ladder networks with overlapping timing so that at no time during the sequence is the constant current source every completely disconnected from at least one of the plurality of ladder networks. The result is that the circuit can be operated at a predetermined duty cycle for time multiplexing purposes.
The invention is also a method of driving a plurality of light emitting diodes using the approach of providing a current to the plurality of light emitting diodes in series circuit. The current is shunted through a switched shunt around any selected diode that is determined to be in a temporarily off, nonemitting condition. The current flowing through the series circuit of light emitting diodes and shunts is maintained constant. As a result, a plurality of light emitting diodes are driven at low power consumption as many diodes share the same current and low noise as the current remains constant regardless of the on or off state of the diodes.
The approach of providing a current and shunting the current around selected ones of the light emitting diodes further comprises the step of providing a current through at least one of a plurality of series circuits of light emitting diodes and controlling the current through each one of the plurality of series circuits of light emitting diodes and corresponding shunts to selectively stop and start the current while simultaneously maintaining current through at least one of the series circuits of LEDs at all times. As a result, the series circuits of LEDs may be driven at different duty cycles for multiplexing purposes without current spikes (and so noise) being created.
Automatic Timing Compensation for a Communication Line
The invention is a method for compensating for line delay variations in a telephone communication system having a single shared communication line comprising the steps of initializing communication on the single line between a control unit and at least one of a plurality of station units coupled by circuit of the line. This compensation is effectively performed by maintaining two separate time bases (transmit and receive) in each communicating device and advancing transmit timing with respect to receive timing (delay receive timing with respect to transmit time). The communication is initialized to a predetermined delay value for transmit advance timing over the receive timing when the system is turned on or powered up. The control unit then performs tests on the system and the predetermined initial value for the line delay is automatically adjusted according to actual line delays sensed on the single communication line. As a result, changes in line delay within the telephone system are automatically accommodated.
The step of automatically adjusting the line delay further comprises the step of automatically measuring capacitance effect and thereby determining approximate capacitance of the single communication line and computing a new transmit advance time to more nearly compensate for line delay with the station units that are connected. There are several types of tests that the control unit can perform in order to determine line capacitance and optimum advance timing. The present design injects a tone signal into one of its transmit channels and test various transmit positions and various settings of its adjustable transmit signal feedback cancellation circuitry, and monitors relative signal level on its receive signal channel. Feedback settings at specific peak and null reading positions are then applied to a lookup table to determine optimum setting of the transmit advance timing.
The step of automatically adjusting the predetermined transmit advance can be performed for each of the plurality of station units coupled to the control unit through the single communication line. A separate automatic adjustment can be made for each station unit, or a single system wide adjustment can be made.
The transmit advance timing can be set by using a static optimal adjustment by independently and optimally adjusting or setting the timing value in each individual communicating device (station unit or control unit) to set a fixed value depending upon its physical position on the wire and its computed best compromise timing relation with all other communicating devices and in particular to the control unit.
The transmit advance can also be adjusted by using a dynamic setting depending upon the communication task at hand for each the station. This is performed by specifically adjusting two particular communicating devices to specific timing adjustments prior to the start of communication between the two for the sole purpose of optimizing that one communication. This might be done for specific troublesome situations or possibly system wide in order to extend the wire length possible for operation or for simply better performance. However, this would be an extremely complicated and time consuming computer task.
A Low Cost Adaptive Echo Balance Methodology
The invention is a circuit for reducing echo back signals on a communication line comprising a summing circuit coupled to the communication line for bidirectional communication of signals therewith. The summing circuit has a summing node. The summing node sums signals which are measures of the transmitted and received signals on the communication line. A balance network circuit couples a selected impedance to the summing node. A processor receives a signal from the summing node and generates a control signal to the balance network circuit to select an impedance to be coupled to the summing node to reduce the signal received from the summing node by the processor circuit. As a result, the echo of a transmitted signal placed on the communication line is substantially reduced.
The balance network circuit comprises a plurality of selectively switched impedance elements. The switched impedance elements are comprised of a plurality of switched capacitive elements and switched resistive elements.
The processor circuit comprises a peak detector circuit for generating a constant analog voltage corresponding to an amplified signal from the summing node. An analog-to-digital converter converts the constant analog voltage to a digital signal. An analog to pulse width circuit can be substituted for the analog to digital circuit to reduce cost. A digital processor receives the digital signal and generates control signals to be coupled to the balance network circuit for altering the impedance of the balance network circuit to minimize the echo back signal.
The circuit further comprises a test tone signal generation circuit for selectively coupling a predetermined test tone on the communication line and into the summing node to generate from the communication line the echo back signals coupled to the summing node.
The circuit further comprises a station unit coupled to the communication line. The control unit communicates with the station unit across the communication line. The station unit similarly is provided with a summing circuit and balance network circuit. The processor circuit corresponding to the control unit communicates control signals to the balance network circuit corresponding to the station unit to substantially reduce the echo back signals at the station unit as determined by optimal reduction of the echo back signals by the processor circuit and corresponding balance network circuit at the control unit.
A Two-Wire Twisted Pair, Multiple Signal, Capacitor Coupled, Communication Line Interface
The invention is a system for coupling to a two-wire communication line to a plurality of sources comprising a plurality of voltage-to-current amplifiers. Each voltage-to-current amplifier is capacitively coupled to the communication line. The voltage-to-current amplifier bidirectionally communicates between the communication line and one of the plurality of sources. A circuit is included for providing high impedance between the plurality of voltage-to-current amplifiers and the communication line. As a result, the plurality of sources are coupled to the communication line without being characterized by the mutual inductance, leakage inductance, inherent resonance, nonlinearity of magnetic media, or the winding resistance characteristic of transformer coupling.
Each of the voltage-to-current amplifiers comprises two differential amplifiers. Each differential amplifier has an output capacitively coupled to one of the communication lines comprising the two-wire communication line. One of the two differential amplifiers is operated as a current source into ground and the other one of the differential amplifiers is operated as a current source from ground.
The system further comprises an RC coupled differential receiving amplifier having two inputs. Each of the inputs is coupled to one of the two wires of the communication line. The differential amplifier has an output characterized by substantial common mode rejection of signals received from the two-wire communication line.
The system further comprises a plurality of echo balance circuits for canceling echo back signals, wherein each the RC coupled differential amplifier has its output coupled to a corresponding one of the echo balance circuits. One of the echo balance circuits is provided for each of the voltage-to-current amplifiers so that echo back signals from each source are substantially reduced.
The system further comprises a balanced DC load powering circuit for allowing line powering over the communication line without lowering the AC impedance apparent to the line and without disturbing signal current information.
The system further comprises a balance load ground circuit for setting a ground reference voltage while maintaining high impedance of the communication line and to allow the plurality of voltage-to-current amplifiers to be coupled to the communication line without significantly lowering the impedance apparent to the communication line due to the interface.
Telephone Line Interface
The invention is a telephone line interface for coupling central office telephone lines with circuitry or systems such as telephones or PBX systems. The interface comprises a transformer having its input coupled to the central office telephone lines and having an output. A load resistor is coupled to the output of the transformer and provides the proper 600 ohm termination to the central office line. An output amplifier receives an audio signal from the circuitry being interfaced to the line. An inverting amplifier is coupled to the output amplifier for inverting the output of the output amplifier and coupling the inverted output to the load resistor. An input amplifier is coupled to the output of the transformer for generating an input signal to the plurality of sources. A balance network is coupled between the output of the output amplifier and the input of the input amplifier for summing the audio signal with the inverted audio signal output through the transformer. The summing is performed at the input of the input amplifier so that echo back signals are substantially reduced by cancellation.
The balancing network has an impedance that simulates the central office lines and equipment. The balance network simulates the output impedance of the transformer as presented to the input amplifier when the transformer is coupled to a telephone central office line and equipment. The balance network can be seen as a circuit for providing a source resistance equivalent to the telephone central office. The telephone line interface thus comprises a circuit for providing an equivalent impedance to a typical transmission telephone line. The telephone line interface therefore comprises a circuit for compensating for the magnetizing inductance of the transformer, for compensating for the load resistance, for compensating for winding resistance of the transformer as it effects low frequency gain of the input amplifier, and for compensating for low frequency cut off associated with magnetizing inductance of the transformer.
A Piezo Driver Using Voltage Doubling and CMOS Techniques
The invention is a circuit for driving a piezo element comprising a first CMOS driver and a second CMOS driver. Each CMOS driver generates a driving voltage in response to an input control voltage. The driving voltages from the two CMOS drivers are placed across the inputs to the piezo element. A circuit is provided for generating two distinct input control voltages opposite in phase. One of the control voltages is coupled to the input of the first CMOS driver and the other one of the control voltages is coupled to the input of the second CMOS driver. As a result, an effective increased voltage swing greater than the magnitude of the supply voltages is experienced across the first and second CMOS drivers and is applied across the piezo element.
Each of the drivers is a CMOS driver having an output equal to alternately the positive or negative supply voltages, Vp or Vn. Each of the CMOS drivers is comprised of a first stage CMOS input driver having an input coupled to the control voltage, and a second stage output CMOS driver. The second stage output CMOS driver has an input coupled to the output of the first stage input driver.
The invention is also a method for generating an improved audio output from a piezo element comprising the steps of providing an input signal having a frequency at which the piezo element is to be driven. This inverted input signal is inverted. The input signal is coupled to a first CMOS driver. An output signal is generated from the first CMOS driver in phase with the inverted input signal coupled to the first CMOS driver. The generated output signal has an amplitude equal to the difference in supply voltage coupled across the first CMOS driver, Vp-Vn. The input signal is coupled to a second CMOS driver. An output signal is generated from the second CMOS driver in phase with the input signal. The output signal generated from the second CMOS driver has a magnitude equal to the difference in voltage supply across the CMOS driver, Vp-Vn. The generated output signals from the first and second CMOS drivers is coupled across the piezo element. As a result, a voltage equal to substantially twice the voltage difference across the CMOS driver is applied across the piezo element to generate increased audio volume.
Voltage Limiter
The invention is a circuit for voltage limiting the output of an amplifier having an input and output. The circuit comprises a first series circuit of bipolar transistors coupled between the input and output of the amplifier. The first series circuit of bipolar transistors is arranged and configured to limit the negative voltage swing of the output. A second series of bipolar transistors is coupled between the input and output of the amplifier. The second series of bipolar transistors is arranged and configured to limit the positive output voltage swing of the amplifier. As a result, voltage limitation of the output of the amplifier is achieved while maintaining high linearity within the useful dynamic range of the amplifier.
The first and second series of bipolar transistors are comprised of a series circuit of a plurality of bipolar transistors. The base and collector of each transistor in the series circuit are coupled in common as the input of the transistor.
Each of the series circuits is comprised of one or more transistors. Each of the transistors within the series circuit, except the end transistors of the series, has the emitter coupled to the base and collector of an adjacent one of the transistors in the series. One end transistor is coupled to the input of the amplifier and the other one of the two end transistors is coupled to the output of the amplifier.
Line Powering for Two-Wire Twisted Pair, Multiple Signal, Capacitor Coupled Communication Line Interface
The invention is a circuit for providing at least one dual voltage supply on an output. The circuit comprises a two-wire communication/power supply line having a positive and negative voltage on the two-wire line. A floating ground circuit provides a floating reference center voltage for the voltage supply to regulate power supplied on the line and isolate the line from ground loop noise.
The floating ground circuit comprises a fixed current source circuit for providing a constant current source having its input coupled to the line and having an output coupled to the output of the supply voltage. An adjustable current source circuit is coupled to the line and to the output of the supply voltage. The output of the adjustable current source circuit is slowly varied to balance the fixed current source circuit to approximately maintain the floating reference center voltage centered between the positive and negative voltages on the two-wire line. The adjustable current source circuit is varied at a rate which is subaudible. The fixed current source is comprised of a voltage regulator and a series output load resistor. The adjustable current source circuit is comprised of a voltage regulator and a variable resistance device.
The floating ground circuit further comprises a voltage divider and a gain stage amplifier. The gain stage amplifier has an input coupled to the voltage divider and an output coupled to the variable resistance device. The voltage divider is coupled between the positive and negative voltages on the two-wire line.
The circuit further comprising a diode bridge. The diode bridge is coupled between the two-wire line and the floating ground circuit. The diode bridge provides a fixed polarity to the floating ground circuit regardless of the nature of coupling between the diode bridge and the line.
In the illustrated embodiment the circuit is used in combination with telephone station units and wherein the floating ground circuit supplies current to telephone station units. The circuit is also used in combination with low powered nontelephonic communication devices in which case the floating ground circuit provides a predetermined and minimum amount of bias current with a small constant current load on the line and to provide linear signaling with the communication devices through the two-wire line.
When used as an adapter box, the floating ground circuit further comprises a diode bridge for providing a predetermined polarity from the line and a fixed current source and voltage divider coupled across the line. The fixed current source is coupled to the voltage divider to provide the floating reference center voltage and to forward bias the diode bridge to maintain operation of the diode bridge in a linear region.
One-Chip System
The invention is also a telephone communication system for communication between a plurality of exterior telephone lines and a single common in house two-wire line. The system comprises a control unit having a chip for coupling to the plurality of exterior telephone lines. The chip controls communication between the plurality of exterior telephone lines and the common two-wire line. A plurality of station/adapter units each have the chip. Each station/adapter unit is coupled remotely throughout the building to the common two-wire line. The chip in each of the station/adapter units selectively communicates with an arbitrarily selected one of the exterior telephone lines under the control of the chip in the control unit. The chip in the control unit and station/adapter unit chips are identical, but operated in different modes according to their respective operational position within the system so that a one-chip system is provided and so that communication on the single common two-wire line is effected without requiring complex control hardware within the control unit or station/adapter units.
The chip in the control unit communicates with the plurality of station/adapter units in a time frame subdivided into a plurality of time slots. A specified portion of each time slot is reserved for communication between the control unit and each one of the plurality of station/adapter units. All communication between each one of the station/adapter units and control unit occurs within the selected portion of the time slot within each time frame.
The system further comprises voice band and digital band interface circuit in the chip for communication between the control unit and the remote station/adapter units.
The system is used in combination with at least one computer having modem communication capability and/or at least one telefax device. The chip is programmable, is capable of communicating signals in telefax compatible format and in telephone tone signal format, and is accessible within the system by extension dialing. The control unit is programmed to selectively couple the computer and/or telefax device coupled to the chip in the station/adapter units to at least one of the plurality of exterior telephone lines through the single common in house two-wire line.
The system is particularly adapted for use with a plurality of the computers and/or telefax devices coupled to the station/adapter units. The control unit selectively couples the plurality of the computers and/or telefax devices into a programmable network.
The station/adaptor unit emulates a telephone receiver with respect to communication characteristics on the plurality of exterior telephone lines. The station/adaptor unit further comprise a circuit for selectively powering the computer and/or telefax device upon is are accessed. The station/adaptor unit also further comprising a modem and a serial input/output port for external communication.
The system further comprises an auxiliary communication device, which is defined to include, but is not limited to a telefax machine, an answering machine, a computer or any other communication or information processing device. The auxiliary communication device has the chip for communication with the system on the single common in house two-wire line.